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| UC1824 UC2824 UC3824 High Speed PWM Controller FEATURES * * * * * * * * * * * Complementary Outputs Practical Operation Switching Frequencies to 1MHz 50ns Propagation Delay to Output High Current Dual Totem Pole Outputs (1.5A Peak) Wide Bandwidth Error Amplifier Fully Latched Logic with Double Pulse Suppression Pulse-by-Pulse Current Limiting Soft Start / Max. Duty Cycle Control Under-Voltage Lockout with Hysteresis Low Start Up Current (1.1 mA) Trimmed Bandgap Reference (5.1V 1%) DESCRIPTION The UC1824 family of PWM control ICs is optimized for high frequency switched mode power supply applications. Particular care was given to minimizing propagation delays through the comparators and logic circuitry while maximizing bandwidth and slew rate of the error amplifier. This controller is designed for use in either currentmode or voltage mode systems with the capability for input voltage feed-forward. Protection circuitry includes a current limit comparator with a 1V threshold, a TTL compatible shutdown port, and a soft start pin which will double as a maximum duty cycle clamp. The logic is fully latched to provide jitter free operation and prohibit multiple pulses at an output. An under-voltage lockout section with 800mV of hysteresis assures low start up current. During under-voltage lockout, the outputs are high impedance. These devices feature totem pole outputs designed to source and sink high peak currents from capacitive loads, such as the gate of a power MOSFET. The on state is designed as a high level. BLOCK DIAGRAM UDG-92034-1 3/97 Powered by ICminer.com Electronic-Library Service CopyRight 2003 ABSOLUTE MAXIMUM RATINGS (Note 1) Supply Voltage (Pins 13, 15) . . . . . . . . . . . . . . . . . . . . . . . . 30V Output Current, Source or Sink (Pins 11, 14) DC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5A Pulse (0.5s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.0A Analog Inputs (Pins 1, 2, 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 7V (Pin 8, 9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V Clock Output Current (Pin 4) . . . . . . . . . . . . . . . . . . . . . . . -5mA Error Amplifier Output Current (Pin 3) . . . . . . . . . . . . . . . . 5mA Soft Start Sink Current (Pin 8) . . . . . . . . . . . . . . . . . . . . . 20mA Oscillator Charging Current (Pin 5) . . . . . . . . . . . . . . . . . . -5mA Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W Storage Temperature Range . . . . . . . . . . . . . . -65C to +150C Lead Temperature (Soldering, 10 seconds) . . . . . . . . . . 300C Note 1: All voltages are with respect to GND (Pin 10); all currents are positive into, negative out of part; pin numbers refer to DIL-16 package. Note 3: Consult Unitrode Integrated Circuit Databook for thermal limitations and considerations of package. CONNECTION DIAGRAMS DIL-16 (Top View) J Or N Package UC1824 UC2824 UC3824 PACKAGE PIN FUNCTION SOIC-16 (Top View) DW Package PLCC-20 & LCC-20 (Top View) Q & L Packages FUNCTION N/C INV NI E/A Out Clock N/C RT CT Ramp Soft Start N/C ILIM/SD Gnd Out Pwr Gnd N/C VC INVOUT VCC VREF 5.1V PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 ELECTRICAL CHARACTERISTICS: Unless otherwise stated,these specifications apply for , RT = 3.65k, CT = 1nF, VCC = 15V, -55C TEST CONDITIONS TJ = 25C, IO = 1mA 10V < VCC < 30V 1mA < IO < 10mA TMIN < TA < TMAX Line, Load, Temperature 10Hz < f < 10kHz TJ = 125C, 1000hrs. VREF = 0V TJ = 25C 10V < VCC < 30V TMIN < TA < TMAX Line, Temperature 5.00 4.95 -15 360 -15 360 340 340 Powered by ICminer.com Electronic-Library Service CopyRight 2003 2 UC1824 UC2824 UC3824 ELECTRICAL CHARACTERISTICS (cont.) PARAMETERS Unless otherwise stated,these specifications apply for , RT = 3.65k, CT = 1nF, VCC = 15V, -55C Oscillator Section (cont.) Clock Out High Clock Out Low Ramp Peak* Ramp Valley* Ramp Valley to Peak* Error Amplifier Section Input Offset Voltage Input Bias Current Input Offset Current Open Loop Gain 1V < VO < 4V CMRR 1.5V < VCM < 5.5V PSRR 10V < VCC < 30V Output Sink Current VPIN 3 = 1V Output Source Current VPIN 3 = 4V Output High Voltage IPIN 3 = -0.5mA Output Low Voltage IPIN 3 = 1mA Unity Gain Bandwidth* Slew Rate* PWM Comparator Section Pin 7 Bias Current VPIN 7 = 0V Duty Cycle Range Pin 3 Zero DC Threshold VPIN 7 = 0V Delay to Output* Soft-Start Section Charge Current VPIN 8 = 0.5V Discharge Current VPIN 8 = 1V Current Limit / Shutdown Section Pin 9 Bias Current 0 < VPIN 9 < 4V Current Limit Threshold Shutdown Threshold Delay to Output Output Section Output Low Level IOUT = 20mA IOUT = 200mA Output High Level IOUT = -20mA IOUT = -200mA Collector Leakage VC = 30V Rise/Fall Time* CL = 1nF Under-Voltage Lockout Section Start Threshold UVLO Hysteresis Supply Current Section Start Up Current VCC = 8V ICC VPIN 1, VPIN 7, VPIN 9 = 0V; VPIN 2 = 1V 2.9 3.0 1.25 2.0 15 3 1 60 75 85 1 -0.5 4.0 0 3 6 0.6 0.1 95 95 110 2.5 -1.3 4.7 0 .5 5.5 12 -1 5.0 1.0 0.6 0.1 95 95 110 2.5 -1.3 4.7 0.5 5.5 12 -1 5.0 1.0 0 1.1 -5 80 80 20 1.25 50 9 0 1.1 -5 85 80 20 1.25 50 9 3 1 3 1 0.9 1.25 1.0 1.40 50 0.25 1.2 13.5 13.0 100 30 9.2 0.8 1.1 22 15 1.1 1.55 80 0.40 2.2 0.9 1.25 1.0 1.40 50 0.25 1.2 13.5 13.0 10 30 9.2 0.8 1.1 22 10 1.1 1.55 80 0.40 2.2 13.0 12.0 13.0 12.0 500 60 9.6 1.2 2.5 33 8.8 0.4 500 60 9.6 1.2 2.5 33 8.8 0.4 * This parameter not 100% tested in production but guaranteed by design. Powered by ICminer.com Electronic-Library Service CopyRight 2003 3 UC1824 Printed Circuit Board Layout Considerations High speed circuits demand careful attention to layout and component placement. To assure proper performance of the UC1824 follow these rules: 1) Use a ground plane. 2) Damp or clamp parasitic inductive kick energy from the gate of driven MOSFETs. Do not allow the output pins to ring below ground. A series gate resistor or a shunt 1 Amp Schottky diode at the output pin will serve this purpose. 3) UC1824 UC2824 UC3824 Bypass VCC, VC, and VREF. Use 0.1F monolithic ceramic capacitors with low equivalent series inductance. Allow less than 1 cm of total lead length for each capacitor between the bypassed pin and the ground plane. 4) Treat the timing capacitor, CT, like a bypass capacitor. Error Amplifier Circuit Simplified Schematic Open Loop Frequency Response Unity Gain Slew Rate Synchronized Operation Two Units in Close Proximity Generalized Synchronization Powered by ICminer.com Electronic-Library Service CopyRight 2003 4 Oscillator Circuit UC1824 UC2824 UC3824 Primary Output Deadtime vs CT (3k RT 100k) Timing Resistance vs Frequency Primary Output Deadtime vs Frequency 160 140 1.0nF TD (ns) 120 100 470pF 80 10k 100k 1M FREQ (Hz) Typical Non-Overlap Time (TNO) Over Temperature 80 70 60 50 40 TNO (ns) 30 20 10 0 -75 -50 -25 0 25 T (C) 50 75 100 125 Non-Overlap Time (TNO) Powered by ICminer.com Electronic-Library Service CopyRight 2003 5 Forward Technique for Off-Line Voltage Mode Application UC1824 UC2824 UC3824 Constant Volt-Second Clamp Circuit The circuit shown here will achieve a constant volt-second product clamp over varying input voltages. The ramp generator components, RT and CR are chosen so that the ramp at Pin 9 crosses the 1V threshold at the same time the desired maximum volt-second product is reached. The delay through the functional nor block must be such that the ramp capacitor can be completely discharged during the minimum deadtime. Output Section Simplified Schematic Rise/Fall Time (CL=1nF) Rise/Fall Time (CL=10nF) Saturation Curves Powered by ICminer.com Electronic-Library Service CopyRight 2003 6 Open Loop Laboratory Test Fixture UC1824 UC2824 UC3824 UDG-92036-2 This test fixture is useful for exercising many of the As with any wideband circuit, careful grounding and byUC1824's functions and measuring their specifications. pass procedures should be followed. The use of a ground plane is highly recommended. UNITRODE CORPORATION 7 CONTINENTAL BLVD. * MERRIMACK, NH 03054 TEL. (603) 424-2410 * FAX (603) 424-3460 Powered by ICminer.com Electronic-Library Service CopyRight 2003 7 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof. Copyright (c) 1999, Texas Instruments Incorporated Powered by ICminer.com Electronic-Library Service CopyRight 2003 |
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